The present invention relates to a semiconductor device, and more particularly to a circuit employing a bipolar transistor and an insulated gate field effect transistor (hereinbelow, termed `IGFET`) which is well-suited to attain a high driving capability and a large output amplitude.
Also, the present invention relates to, in a driving circuit including a bipolar transistor, especially to a driving circuit which is well-suited to reliably prevent the saturation of the bipolar transistor and to set an `off` level at will and at high precision.
As a circuit employing a bipolar transistor and an IGFET, there has heretofore been a semiconductor device disclosed in the official gazette of Japanese Patent Application Laid-open No. 59-25423.
FIG. 1A is a circuit diagram of the semiconductor device. The operation of the circuit and the problem thereof will be explained with reference to FIG. 1A. This semiconductor device consists of the parallel connection between a circuit composed of CMOS (complementary MOS) transistors 4, 5 and a bipolar transistor 7 and a circuit composed of an IGFET 6 and a bipolar transistor 8. In the ensuing explanation, the voltage V.sub.SS of a lower source shall be assumed 0 V. When the potential of an input node I is 0 V, the P-channel IGFET 4 turns "on" and current flows to the base of the bipolar transistor 7, so that this bipolar transistor 7 turns "on". On the other hand, the bipolar transistor 8 does not turn "on" because the potential of the base thereof is 0 V. As a result, current flows to an output node O, the potential of which rises. The potential of the output node O finally becomes a value which is obtained by subtracting the base-emitter forward voltage V.sub.BE of the bipolar transistor 7 from the voltage V.sub.CC of an upper source. In this manner, with the prior-art circuit shown in FIG. 1A, the potential of the output node O does not rise up to the voltage V.sub.CC of the upper source.
Besides the circuit stated above, there has been driving circuitry disclosed in the official gazette of Japanese Patent Application Laid-open No. 59-8431 as a semiconductor device constructed of a circuit in which IGFETs and bipolar transistors are combined.
FIG. 1B is a diagram showing the circuit arrangement of the semiconductor device. The circuit in FIG. 1B is such that circuits composed of symmetrically arranged CMOS inverter circuits and bipolar transistors are connected in parallel across input and output nodes. The foregoing circuit in FIG. 1A delivers a signal having an inverted phase to the phase of an input, whereas the circuit in FIG. 1B delivers a signal having the same phase as that of an input. More specifically, when the input node I becomes a high level, an IGFET 13 turns "on" and current flows to the base of a bipolar transistor 17, so that this bipolar transistor 17 turns "on". Meanwhile, a P-channel IGFET 15 turns "off" and an N-channel IGFET 16 turns "on", so that the base potential of a bipolar transistor 18 becomes 0 V to turn "off" this bipolar transistor 18. As a result, current flows to the output node O, the potential of which rises. At this time, the potential of the output node O rises up to a value V.sub.CC -V.sub.T -V.sub.BE which is obtained by subtracting the threshold voltage V.sub.T of the N-channel IGFET 13 and the base-emitter forward voltage V.sub.BE of the bipolar transistor 17 from an upper source voltage V.sub.CC. In this manner, the output level of the circuit in FIG. 1B becomes still lower than the output level in FIG. 1A.
As another example of driving circuitry constructed including a bipolar transistor, a circuit shown in FIG. 1C is disclosed in the official gazette of Japanese Patent Application Laid-open No. 59-8431. In this circuit, when an input node I becomes a low potential, a base current flows from a power source V.sub.CC to a bipolar transistor Q.sub.2A through a P-channel IGFET M.sub.2A, to turn "on" the transistor Q.sub.2A, so that an output node O becomes a high level. Besides, when the input node I becomes a high potential, an N-channel IGFET M.sub.2C turns "on", and a base current flows to a bipolar transistor Q.sub.2B to turn "on" this transistor Q.sub.2B, so that the output node O becomes a low level. In this circuit, the collector of the bipolar transistor Q.sub.2A and the source of the P-channel IGFET M.sub.2A are connected. For this reason, when the bipolar transistor Q.sub.2A turns "on", the base potential thereof rises from a low potential near 0 V to the potential of the power source V.sub.CC. Meanwhile, when the collector current of the bipolar transistor Q.sub.2A begins to flow, the collector potential thereof becomes lower than the potential of the power source V.sub.CC by the product between the collector current and a parasitic collector resistance in the bipolar transistor Q.sub.2A and a resistance parasitic to external collector wiring (both being omitted from illustration for the sake of brevity). Accordingly, when the collector resistance of the bipolar transistor Q.sub.2A is great, the base potential of this transistor Q.sub.2A might become higher than the collector potential thereof to establish the so-called saturation state. As is well known, when the bipolar transistor falls into the saturation state, large quantities of minority carriers are stored in the base, and a long time is required for turn-off. This causes a problem that a through current increases when the input I changes-over from the low level to the high level in the above operation. Next, the "off" level of the circuit in FIG. 1C will be considered. In this circuit, when the input node I has become the low level, the potential of the output node O begins to rise, and it finally rises up to a value which is obtained by subtracting the base-emitter forward voltage V.sub.BE of the bipolar transistor Q.sub.2A from the potential of the power source V.sub.CC. In order to set the potential of the "off" level, accordingly, the potential of the power source V.sub.CC needs to be changed. Since, however, the power source V.sub.CC needs to feed the collector current of the bipolar transistor Q.sub.2A besides the base current thereof as described above, it requires a great capability of current supply, and it has been difficult to set the magnitude at will and at high precision.
To sum up, the following problems are revealed:
(1) The voltage of the output node O does not rise up to the upper source voltage V.sub.CC. Since the low output voltage becomes a low input level for a succeeding circuit, the operation of the succeeding circuit slows, and the feature of high operating speed of the bipolar transistor cannot be satisfactorily achieved. In addition, this problem becomes acute when the microminiaturization of a device makes it necessary to lower a source voltage. Accordingly, a circuit is desired which can provide a sufficiently high output level while satisfactorily keeping the high driving capability of the bipolar transistor.
(2) The voltage of the high potential side of the input node I needs to be maintained at or above V.sub.CC -.vertline.V.sub.TP .vertline. for the purpose of preventing a through current from flowing. Here, V.sub.TP denotes the threshold voltage of the P-channel IGFET. This signifies that, when the high level of the input voltage is lowered for the reduction of power consumption or the microminiaturization of the device, also the source voltage V.sub.CC must be inevitably lowered in order to prevent the through current. Consequently, the output voltage lowers still more.
(3) The bipolar transistor may saturate, and it has been difficult to set the value of the "off" level at will.